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EDWin XP - Model Generators

The model generators allow converting VHDL source files to models for simulation purposes. Since EDWin XP supports two forms of simulation Mixed Mode and EDSpice, two model generators have been included MM Simulation Model Generator and EDSpice Simulation Model Generator.
 
Model Generator for Mixed Mode Simulator

This tool converts a vhdl source file to a simulatable component in EDWin XP. This also serves the purpose of making simulation much faster.
Since VHDL can be used to create digital models, digital simulation primitives can be created using MM Simulation Model Generator. Earlier, the only way of creating simulation primitives was to model the behaviour of the particular component using Visual C++. Knowledge of programming is naturally not expected of electronic engineers and the need for developing a tool arose which could make creation of models easier.

Model Generator for EDSpice Simulator

This tool converts a vhdl source file to a simulatable component in EDSpice, the SPICE based simulator of EDWinXP. This also serves the purpose of making simulation much faster.
Since VHDL can only be used to create digital models, only digital simulation models can be created using EDSpice Simulation Model Generator.

Note: EDComX and EDPrimX are tools which can be used for creating both analog and digital models, however it assumes programming knowledge and the user has to build his own simulation primitive dll.

 

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