for EDSpice Simulator
This tool converts a vhdl source file to a
simulatable component in EDSpice, the SPICE based simulator of EDWinXP.
This also serves the purpose of making simulation much faster.
Since VHDL can only be used to create digital models, only digital
simulation models can be created using EDSpice Simulation Model
and EDPrimX are tools which can be used for creating both analog and
digital models, however it assumes programming knowledge and the user
has to build his own simulation primitive dll.